Job Description

Design Enablement team at India, is part of Technology Development group, having charter to develop methodology for advance process nodes, providing opportunity, to be among the first one to work on latest technology. This role, will provide opportunity to work on Physical design, using Synthesis -Automatic Placement and Route flow, from RTL to GDS , including sign off for Timing, Reliability and Layout verification, using Industry standard tools for complex APR partitions with high frequency targets. Candidate will be working on wide variety of activities related to Synthesis, Floor planning, Placement, Clock Tree Synthesis, Routing, Timing convergence, Scan, Hard Macro integration, and Physical convergence. They will work on constraint development, flow optimization to meet design requirements, by working with RTL developers, CAD team and EDA vendors. This role requires good understanding of devices, digital circuits and timing concepts.

Qualifications

Candidate must have Master's degree (M.Tech/MS) in Microelectronics/VLSI/ Electronics Engineering or equivalent qualification from reputed institute. Candidate should have good knowledge of VLSI, Digital electronics and understanding of semiconductor devices, digital circuits, timing closure of design. Understanding of fabrication and process technology will be added advantage. Any scripting language experience, like perl, TCL, python would be plus point. Candidate should have good analytical, problem-solving skill for debugging issues faced at work and should have proactive and transparent communication. They should be having mindset to work in diverse and collaborative environment with teams in different domains and Geos.